900,000+ datasheet pdf search and download

Datasheet4U offers most rated semiconductors data sheet pdf






Hyundai

HY5DU281622 Datasheet Preview

HY5DU281622 Datasheet

4 Banks x 2M x 16Bit Double Data Rate SDRAM

No Preview Available !

DESCRIPTION
HY5DU281622
4 Banks x 2M x 16Bit Double Data Rate SDRAM
PRELIMINARY
The Hyundai HY5DU281622 is a 134,217,728-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited
for the main memory applications which require large memory density and high bandwidth. HY5DU281622 is orga-
nized as 4 banks of 2,097,152x16.
HY5DU281622 offers fully synchronous operations referenced to both rising and falling edges of the clock. While all
addresses and control inputs are latched on the rising edges of the clock(falling edges of the CLK), Data(DQ), Data
strobes(LDQS/UDQS) and Write data masks(LDM/UDM) inputs are sampled on both rising and falling edges of it. The
data paths are internally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage
levels are compatible with SSTL_2.
Mode Register set options include the length of pipeline (CAS latency of 2 / 2.5 ), the number of consecutive read or
write cycles initiated by a single control command (Burst length of 2 / 4 / 8), the burst count sequence(sequential or
interleave), DQ FET Control (/QFC) and Output Driver types (Full / Half Strength Driver). Because data rate is doubled
through reading and writing at both rising and falling edges of the clock, 2X higher data bandwidth can be achieved
than that of traditional (single data rate) Synchronous DRAM.
FEATURES
• 2.5V VDD and VDDQ power suppliy
• All inputs and outputs are compatible with SSTL_2
interface
• Delay Locked Loop(DLL) installed with DLL reset
mode
• Write mask byte controlled by LDM and UDM
• JEDEC standard 400mil 66pin TSOP-II with 0.65mm • Bytewide data strobes by LDQS and UDQS
pin pitch
• Programmable CAS Latency 2 and 2.5 supported
• Fully differential clock operations(CLK & CLK) with
100MHz/125MHz/133MHz
• Write Operations with 1 Clock Write Latency
• All addresses and control inputs except Data, Data
• /QFC & Half Strength Driver controlled by EMRS
strobes and Data masks latched on the rising edges • Programmable Burst Length 2 / 4 / 8 with both
of the clock
sequential and interleave mode
• Data(DQ) and Write masks(LDM/UDM) latched on
both rising and falling edges of the Data Stobe
• Data outputs on LDQS/UDQS edges when read
(edged DQ) Data inputs on LDQS/UDQS centers
when write (centered DQ)
• Internal four bank operations with single pulsed RAS
• Auto refresh and self refresh supported
• 4096 refresh cycles / 64ms
ORDERING INFORMATION
Part No.
HY5DU281622(L)T-K
HY5DU281622(L)T-H
HY5DU281622(L)T-L
* (L) Low Power Part
Power Suppy
VDD=2.5V
VDDQ=2.5V
Clock Frequency
143MHz (*PC266A)
133MHz (*PC266B)
125MHz (*PC200)
Organization
Interface Package
4Banks
x 2Mbit x 16
SSTL_2
400mil 66pin
TSOP II
* JEDEC Defined Specifications compliant
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 1.2 / Mar.00




Hyundai

HY5DU281622 Datasheet Preview

HY5DU281622 Datasheet

4 Banks x 2M x 16Bit Double Data Rate SDRAM

No Preview Available !

PIN CONFIGURATION
PIN DESCRIPTION
VDD 1
66 VSS
DQ0 2
TOP VIEW
65 DQ15
VDDQ 3
64 VSSQ
DQ1 4
63 DQ14
DQ2 5
62 DQ13
VSSQ 6
61 VDDQ
DQ3 7
60 DQ12
DQ4 8
59 DQ11
VDDQ 9
58 VSSQ
DQ5 10
57 DQ10
DQ6 11
56 DQ9
VSSQ 12
55 VDDQ
DQ7 13
54 DQ8
NC 14
53 NC
VDDQ 15 400mil X 875mil 52 VSSQ
LDQS 16 66 Pin TSOP-II 51 UDQS
NC 17 0.65mm Pin Pitch 50 NC
VDD 18
49 VREF
/QFC, NC 19
48 VSS
LDM 20
47 UDM
/WE 21
46 /CLK
/CAS 22
45 CLK
/RAS 23
44 CKE
/CS 24
43 NC
NC 25
42 NC
BA0 26
41 A11
BA1 27
40 A9
A10/AP 28
39 A8
A0 29
38 A7
A1 30
37 A6
A2 31
36 A5
A3 32
35 A4
VDD 33
34 VSS
HY5DU281622
PIN
CLK, CLK
CKE
CS
BA0, BA1
A0 ~ A11
RAS, CAS, WE
LDM, UDM
LDQS, UDQS
DQ0 ~ DQ15
VDD/VSS
VDDQ/VSSQ
VREF
/QFC (optional)
NC
PIN NAME
Differential Clock Input
Clock Enable
Chip Select
Bank Select Address
Address
Row Address Strobe,
Column Address Strobe,
Write Enable
Write Mask
Data Input/Output Strobe
Data Input/Output
Power Supply/Ground
Data Output Power/Ground
Reference Voltage
DQ FET Switch Control
No Connection
DESCRIPTION
The system clock input. All of the inputs are latched on the rising edges of the
clock except DQi, LDQS/UDQS and LDM/UDM that are sampled on the both.
Controls internal clock signal and when deactivated, the DDR SDRAM will be
one of the states among power down, suspend or self refresh.
Enables or disables all inputs except CLK/CLK, CKE, L/UDQS and L/UDM.
Selects bank to be activated during either RAS or CAS activity.
Selects bank to be read/written during either RAS or CAS activity.
Row Address : A0 ~ A11, Column Address : A0 ~ A8, AP Flag : A10
RAS, CAS and WE define the operations.
Refer function truth table for details.
Masks input data in write mode.
Active on the both edges for Data Input and Output.
Multiplexed data input / output pin.
Power supply for internal circuits and input buffers.
Power supply for output buffers for Noise immunity.
Reference voltage for inputs for SSTL interface.
Controls FET Switches on DQs used for reduction of Impedance.
No connection.
Rev. 1.2 / Mar.00
2


Part Number HY5DU281622
Description 4 Banks x 2M x 16Bit Double Data Rate SDRAM
Maker Hyundai
PDF Download

HY5DU281622 Datasheet PDF






Similar Datasheet

1 HY5DU281622 4 Banks x 2M x 16Bit Double Data Rate SDRAM
Hyundai
2 HY5DU281622AT (HY5DU28xxxAT) 3rd 128M DDR SDRAM
Hynix Semiconductor
3 HY5DU281622AT-6 128M(8Mx16) DDR SDRAM
Hynix Semiconductor
4 HY5DU281622DT (HY5DU28xx22D(L)T) 128Mb-S DDR SDRAM
Hynix Semiconductor
5 HY5DU281622ET 128M(8Mx16) GDDR SDRAM
Hynix Semiconductor
6 HY5DU281622FTP 128Mb DDR SDRAM
Hynix
7 HY5DU281622LT (HY5DU28xxxAT) 3rd 128M DDR SDRAM
Hynix Semiconductor
8 HY5DU281622LT (HY5DU28xx22D(L)T) 128Mb-S DDR SDRAM
Hynix Semiconductor
9 HY5DU281622LT-H 4 Banks x 2M x 16Bit Double Data Rate SDRAM
Hyundai





Part Number Start With

0    1    2    3    4    5    6    7    8    9    A    B    C    D    E    F    G    H    I    J    K    L    M    N    O    P    Q    R    S    T    U    V    W    X    Y    Z



Site map

Webmaste! click here

Contact us

Buy Components

Privacy Policy