HY5DU281622 Datasheet PDF - Hyundai 4 Banks x 2M x 16Bit Double Data Rate SDRAM Specs

HY5DU281622 - 4 Banks x 2M x 16Bit Double Data Rate SDRAM

Datasheet Summary

Description

The Hyundai HY5DU281622 is a 134,217,728-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for the main memory applications which require large memory density and high bandwidth.

HY5DU281622 is organized as 4 banks of 2,097,152x16.

Features

2.5V V DD and VDDQ power suppliy All inputs and outputs are compatible with SSTL_2 interface JEDEC standard 400mil 66pin TSOP-II with 0.65mm pin pitch Fully differential clock operations(CLK & CLK) with 100MHz/125MHz/133MHz All addresses and control inputs except Data, Data strobes and Data masks latched on the rising edges of the clock Data(DQ) and Write masks(LDM/UDM) latched on both rising and falling edges of the Data Stobe Data outputs on LD.

Datasheet Details

Part number	HY5DU281622
Manufacturer	Hyundai
File Size	83.14 KB
Description	4 Banks x 2M x 16Bit Double Data Rate SDRAM
Datasheet	HY5DU281622 Datasheet
Additional preview pages of the HY5DU281622 datasheet.

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Full PDF Text Transcription

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HY5DU281622 4 Banks x 2M x 16Bit Double Data Rate SDRAM PRELIMINARY DESCRIPTION The Hyundai HY5DU281622 is a 134,217,728-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for the main memory applications which require large memory density and high bandwidth. HY5DU281622 is organized as 4 banks of 2,097,152x16. HY5DU281622 offers fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the clock(falling edges of the CLK), Data(DQ), Data strobes(LDQS/UDQS) and Write data masks(LDM/UDM) inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 2-bit prefetched to achieve very high bandwidth.

Published: Aug 4, 2014 |