ICS85454-01 Datasheet | Integrated Circuit Systems

Integrated Circuit Systems, Inc. DUAL 2:1/1:2 DIFFERENTIAL-TO-LVDS MULTIPLEXER Features - Dual 2:1/1:2 MUX - Three LVDS outputs - Three differential inputs - Differential inputs can accept the following differential levels: LVPECL, LVDS, CML - Loopback test mode available - Maximum output frequency: 2.5GHz - Part-to-part skew: 250ps (maximum) - Additive phase jitter, RMS: 0.05ps (typical) - Propagation delay: 550ps (maximum) - 2.5V operating supply - -40°C to 85°C ambient operating temperature - Available in both standard and lead-free Ro HS pliant packages GENERAL DESCRIPTION The ICS85454-01 is a 2:1/1:2 Multiplexer and a member of the Hi Per Clock STM family of high Hi Per Clock S™ performance clock solutions from ICS. The 2:1 Multiplexer allows one of 2 inputs to be selected onto one output pin and the 1:2 MUX switches one input to both of two outputs. This device may be useful for multiplexing multi-rate Ethernet PHYs which have 100Mbit and 1000Mbit transmit/receive pairs onto an optical SFP module which has a single transmit/receive pair. Another mode allows loop back testing and allows the output of a PHY transmit pair to be .. routed to the PHY input pair. For examples, please refer to the Application Information section of the data sheet. IC S The ICS85454-01 is optimized for applications requiring very high performance and has a maximum operating frequency in 2.5GHz. The device is packaged in a small, 3mm x 3mm VFQFN package, making it ideal for use on space-constrained boards. BLOCK DIAGRAM SELB PIN ASSIGNMENT SELA n QB VDD QB INA0 n INA0 QA0 1 n QA0 2 INB n INB 16 15 14 13 12 11 10 9 5 INA0 n INA0 INA1 n INA1 LOOP0 QA0 n QA0 QA1 3 n QA1 4 6 n...