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Integrated Device Technology Electronic Components Datasheet

IDT71V509 Datasheet

128K x 8 3.3V SYNCHRONOUS SRAM WITH ZBTO AND FLOW-THROUGH OUTPUT

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Integrated Device Technology, Inc.
128K x 8 3.3V SYNCHRONOUS SRAM
WITH ZBTAND FLOW-THROUGH
OUTPUT
ADVANCE
INFORMATION
IDT71V509
FEATURES:
• 128K x 8 memory configuration
• High speed - 66 MHz (9 ns Clock-to-Data Access)
• Flow-Through Output
• No dead cycles between Write and Read Cycles
• Low power deselect mode
• Single 3.3V power supply (±5%)
• Packaged in 44-lead SOJ
DESCRIPTION:
The IDT71V509 is a 3.3V high-speed 1,024,576-bit syn-
chronous SRAM organized as 128K x 8. It is designed to
eliminate dead cycles when turning the bus around between
reads and writes, or writes and reads. Thus, it has been given
the name ZBT, or Zero Bus Turnaround.
Addresses and control signals are applied to the SRAM
during one clock cycle, and one clock cycle later its associated
data cycle occurs, be it read or write.
The IDT71V509 contains data, address, and control signal
registers. Output Enable is the only asynchronous signal, and
can be used to disable the output at any time.
A Clock Enable (CEN) pin allows operation of the IDT71V509
to be suspended as long as necessary. All synchronous
inputs are ignored when CEN is high. A Chip Select (CS) pin
allows the user to deselect the device when desired. If CS is
high, no new memory operation is initiated, but any pending
data transfers (reads and writes) will still be completed.
The IDT71V509 utilizes IDT's high-performance 3.3V CMOS
process, and is packaged in a JEDEC Standard 400-mil 44-
lead small outline J-lead plastic package (SOJ) for high board
density.
FUNCTIONAL BLOCK DIAGRAM
Address
DQ
Control
(WE, CS, CEN)
DQ
Address
SRAM
Control
DI DO
DQ
Control Logic
Clk
Mux Sel
Clock
OE Gate
Data
The IDT logo is a registered trademark and CacheRAM, Zero Bus Turnaround and ZBTare trademarks of Integrated Device Technology, Inc.
Pentium is a trademark of Intel Corp.
PowerPC is a trademark of International Business Machines, Inc.
COMMERCIAL TEMPERATURE RANGE
©1996 Integrated Device Technology, Inc.
11.3
3618 drw 01
AUGUST 1996
DSC-3618/1
1


Integrated Device Technology Electronic Components Datasheet

IDT71V509 Datasheet

128K x 8 3.3V SYNCHRONOUS SRAM WITH ZBTO AND FLOW-THROUGH OUTPUT

No Preview Available !

IDT71V509
128K x 8 3.3V SYNCHRONOUS SRAM WITH ZBTAND FLOW-THROUGH OUTPUT
PIN CONFIGURATION
COMMERCIAL TEMPERATURE RANGE
A0
A1
A2
VSS
I/O7
I/O6
VDD
I/O5
I/O4
OE
VDD
VSS
VSS
I/O3
I/O2
VDD
I/O1
I/O0
VSS
NC (2)
A3
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
SO44-1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
NC (4)
A16
A15
A14
A13
A12
A11
WE
VDD(5)
CLK
VSS
VDD
NC (1)
CS
CEN
A10
A9
A8
A7
A6
A5
NC(3)
Notes:
1. Pin 32: Future control input
2. Pin 20: Future I/O8
3. Pin 23: Future A17
4. Pin 44: Future A18
5. Pin 36 does not need to be connected directly to VDD, as long as it is VIH.
TOP VIEW
3618 drw 02
PIN DEFINITIONS(1)
Symbol
Pin Function
A0-A16
Address Inputs
CLK
CEN
Clock
Clock Enable
I/O
I
I
I
CS
Chip Select
I
WE
Write Enable
I
OE
Output Enable
I
I/O0-I/O7 Data Input/Output I/O
VDD
VSS
Power Supply
Ground
N/A
N/A
Active
N/A
N/A
LOW
LOW
LOW
LOW
N/A
N/A
N/A
Description
Synchronous Address inputs. The address is registered on every rising edge
of CLK if CEN and CS are both low.
The clock input. Except for OE, all input and output timing references for the
device are with respect to the rising edge of CLK.
Synchronous clock enable input. When CEN is sampled high, the other
synchronous inputs are ignored, and outputs remain unchanged. When CEN
is sampled low, the IDT71V509 operates normally.
Synchronous chip select input. When CS is sampled low, the device operates
normally. When CS is sampled high, no read or write operation is initiated,
and the I/O bus is tri-stated the next cycle. CS is ignored if CEN is high at
the same rising edge of CLK.
Synchronous write enable. If WE is sampled low, a write is initiated at the
address that is registered at that time. If WE is sampled high, a read is initiated
at the address that is registered at that time. WE is ignored when either CEN
or CS is sampled high.
Asynchronous output enable. When OE is high, the I/O bus goes high
impedance. OE must be low to read data from the IDT71V509.
Synchronous data input/output (I/O) pins. Both the data input path and data
output path are registered and triggered by the rising edge of CLK.
3.3V power supply pins.
Ground pins.
11.3 2


Part Number IDT71V509
Description 128K x 8 3.3V SYNCHRONOUS SRAM WITH ZBTO AND FLOW-THROUGH OUTPUT
Maker Integrated Device Technology
Total Page 9 Pages
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