SY89873L Description
< 800ps tPD (matched-delay between banks) < 15ps within-device skew This 3.3V low-skew, low-jitter, precision LVDS output clock < 190ps rise/fall time divider accepts any high-speed differential clock input (AC- or Low jitter design DC-coupled) CML, LVPECL, HSTL or LVDS and divides down < 1psRMS cycle-to-cycle jitter the frequency using a programmable divider ratio to create a < 10psPP total jitter frequency-locked,...
SY89873L Applications
- 3.3V power supply Edge® timing and distribution family. For 2.5V applications, consider the SY89872U. For applications that require an
- Wide operating temperature range: -40°C to +85°C LVPECL output, consider the SY89871U