MPC992
features to aid in system debug and test. The PECL reference input pins can be interfaced to a test signal and the PLL can be bypassed to allow the designer to drive the MPC992 outputs directly. This allows for single stepping in a system functional debug mode. In addition an overriding reset is provided which will force all of the Q outputs LOW upon assertion. The MPC992 is packaged in a 32- lead TQFP package to optimize both performance and board density.
MPC992 LOGIC DIAGRAM
PLL_EN VCO_SEL XTAL_SEL XTAL1 XTAL2 PECL_CLK PECL_CLK FSEL0 FSEL1 POR XTAL OSC x2 1 0 Integrated PLL 0 1 0 1
Qan Qan Frequency Generator Qbn Qbn SYNC SYNC
(x4)
(x3)
Reset
(x1)
7/96
© Motorola, Inc. 1996
REV 1
VCCO1 VCCO2 17 16 15 14 13 Qb0 Qb0 Qb1 Qb1 Qb2 Qb2 PLL_EN GNDI 12 11 10 9 1 2 3 4 5 6 7 8 XTAL2 SYNC 19 PECL_CLK SYNC 18 XTAL1
Qa2
Qa2
Qa3 21 XTAL_SEL
24 Qa1 Qa1 Qa0 Qa0 GNDA VCCA Reset VCCI 25 26 27 28
29 30 31 32
FUNCTION TABLE 1
FSEL0 0 0 1 1 FSEL1 0 1 0 1 Qa...
