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MPC992 - LOW VOLTAGE PLL CLOCK DRIVER

General Description

Pin Name VCO_SEL PLL_EN XTAL_SEL XTAL1:2 PECL_CLK PECL_CLK FSELn RESET Function VCO range select pin (Int Pullup) PLL bypass select pin (Int Pullup) Input reference source select pin (Int Pullup) Crystal interface pins for the internal oscillator True PECL reference clock input (Int Pulldown) Compli

Key Features

  • to aid in system debug and test. The PECL reference input pins can be interfaced to a test signal and the PLL can be bypassed to allow the designer to drive the MPC992 outputs directly. This allows for single stepping in a system functional debug mode. In addition an overriding reset is provided which will force all of the Q outputs LOW upon assertion. The MPC992 is packaged in a 32.
  • lead TQFP package to optimize both performance and board density. MPC992 LOGIC.

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MOTOROLA SEMICONDUCTOR TECHNICAL DATA Low Voltage PECL PLL Clock Driver The MPC992 is a 3.3V compatible, PLL based PECL clock generator and distributor. The fully differential design ensures optimum skew and PLL jitter performance. The performance of the device makes the MPC992 ideal for workstations, main frame computer, telecommunication and instrumentation applications. The device offers a crystal oscillator or a differential PECL reference clock input to provide flexibility in the reference clock interface. All of the control signals to the MPC992 are LVTTL compatible inputs. MPC992 LOW VOLTAGE PLL CLOCK DRIVER • • • • • • • Fully Integrated PLL Output Frequency of up to 400MHz PECL Clock Inputs and Outputs Operates from a 3.