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Motorola Electronic Components Datasheet

MTB30N06VL Datasheet

TMOS POWER FET

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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
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by MTB30N06VL/D
Designer's Data Sheet
TMOS V
Power Field Effect Transistor
D2PAK for Surface Mount
N–Channel Enhancement–Mode Silicon Gate
TMOS V is a new technology designed to achieve an on–resistance
area product about one–half that of standard MOSFETs. This new
technology more than doubles the present cell density of our 50
and 60 volt TMOS devices. Just as with our TMOS E–FET designs,
TMOS V is designed to withstand high energy in the avalanche and
commutation modes. Designed for low voltage, high speed
switching applications in power supplies, converters and power
motor controls, these devices are particularly well suited for bridge
circuits where diode speed and commutating safe operating areas
are critical and offer additional safety margin against unexpected
voltage transients.
New Features of TMOS V
On–resistance Area Product about One–half that of Standard
MOSFETs with New Low Voltage, Low RDS(on) Technology
Faster Switching than E–FET Predecessors
Features Common to TMOS V and TMOS E–FETs
Avalanche Energy Specified
IDSS and VDS(on) Specified at Elevated Temperature
Static Parameters are the Same for both TMOS V and
TMOS E–FET
Surface Mount Package Available in 16 mm 13–inch/2500 Unit
Tape & Reel, Add T4 Suffix to Part Number
G
MTB30N06VL
Motorola Preferred Device
TMOS POWER FET
30 AMPERES
60 VOLTS
RDS(on) = 0.050 OHM
TM
D
CASE 418B–02, Style 2
S D2PAK
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Rating
Symbol
Value
Unit
Drain–to–Source Voltage
Drain–to–Gate Voltage (RGS = 1.0 M)
Gate–to–Source Voltage — Continuous
Gate–Source Voltage — Non–Repetitive (tp 10 ms)
VDSS 60 Vdc
VDGR 60 Vdc
VGS
± 15 Vdc
VGSM ± 20 Vpk
Drain Current — Continuous
Drain Current — Continuous @ 100°C
Drain Current — Single Pulse (tp 10 µs)
Total Power Dissipation
Derate above 25°C
Total Power Dissipation @ TA = 25°C (1)
Operating and Storage Temperature Range
Single Pulse Drain–to–Source Avalanche Energy — STARTING TJ = 25°C
(VDD = 25 Vdc, VGS = 5 Vdc, PEAK IL = 30 Apk, L = 0.342 mH, RG = 25 )
ID
ID
IDM
PD
TJ, Tstg
EAS
30
20
105
90
0.6
3.0
– 55 to 175
154
Adc
Apk
Watts
W/°C
Watts
°C
mJ
Thermal Resistance — Junction to Case
Thermal Resistance — Junction to Ambient
Thermal Resistance — Junction to Ambient (1)
RθJC
RθJA
RθJA
1.67 °C/W
62.5
50
Maximum Lead Temperature for Soldering Purposes, 1/8from Case for 10 seconds
(1) When surface mounted to an FR4 board using the minimum recommended pad size.
TL 260 °C
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
Designer’s is a trademark of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Thermal Clad is a trademark of the Bergquist Company.
REV 4
© MMoototororloa,laIncT.M19O96S Power MOSFET Transistor Device Data
1


Motorola Electronic Components Datasheet

MTB30N06VL Datasheet

TMOS POWER FET

No Preview Available !

MTB30N06VL
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Characteristic
Symbol Min Typ Max Unit
OFF CHARACTERISTICS
Drain–to–Source Breakdown Voltage
(VGS = 0 Vdc, ID = 250 µAdc)
Temperature Coefficient (Positive)
V(BR)DSS
60 — — Vdc
— 63 — mV/°C
Zero Gate Voltage Drain Current
(VDS = 60 Vdc, VGS = 0 Vdc)
(VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150°C)
Gate–Body Leakage Current (VGS = ± 15 Vdc, VDS = 0 Vdc)
ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 µAdc)
Threshold Temperature Coefficient (Negative)
IDSS
IGSS
µAdc
— — 10
— — 100
— — 100 nAdc
VGS(th)
1.0 1.5 2.0 Vdc
— 4.0 — mV/°C
Static Drain–to–Source On–Resistance (VGS = 5 Vdc, ID = 15 Adc)
Drain–to–Source On–Voltage
(VGS = 5 Vdc, ID = 30 Adc)
(VGS = 5 Vdc, ID = 15 Adc, TJ = 150°C)
Forward Transconductance (VDS = 6.25 Vdc, ID = 15 Adc)
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
Transfer Capacitance
(VDS = 25 Vdc, VGS = 0 Vdc,
f = 1.0 MHz)
SWITCHING CHARACTERISTICS (2)
Turn–On Delay Time
Rise Time
Turn–Off Delay Time
Fall Time
(VDD = 30 Vdc, ID = 30 Adc,
VGS = 5 Vdc,
RG = 9.1 )
Gate Charge
(See Figure 8)
(VDS = 48 Vdc, ID = 30 Adc,
VGS = 5 Vdc)
SOURCE–DRAIN DIODE CHARACTERISTICS
Forward On–Voltage
(IS = 30 Adc, VGS = 0 Vdc)
(IS = 30 Adc, VGS = 0 Vdc, TJ = 150°C)
RDS(on)
VDS(on)
gFS
Ciss
Coss
Crss
td(on)
tr
td(off)
tf
QT
Q1
Q2
Q3
VSD
— 0.033 0.05 Ohms
Vdc
— 1.1 1.8
— — 1.73
13 21 — Mhos
1130
1580
pF
— 360 500
— 95 190
— 14 30 ns
— 260 520
— 54 110
— 108 220
— 27 40 nC
—5—
— 17 —
— 15 —
Vdc
— 0.98 1.6
— 0.89 —
Reverse Recovery Time
(IS = 30 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/µs)
Reverse Recovery Stored Charge
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from the drain lead 0.25from package to center of die)
trr
ta
tb
QRR
LD
— 86 —
— 49 —
— 37 —
— 0.228 —
— 4.5 —
ns
µC
nH
Internal Source Inductance
(Measured from the source lead 0.25from package to source bond pad)
LS
nH
— 7.5 —
(1) Pulse Test: Pulse Width 300 µs, Duty Cycle 2%.
(2) Switching characteristics are independent of operating junction temperature.
2 Motorola TMOS Power MOSFET Transistor Device Data


Part Number MTB30N06VL
Description TMOS POWER FET
Maker Motorola
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