S7A321830M Datasheet | NETSOL

Features - VDD = 1.8V (1.7V ~ 2.0V) or 2.5V (2.3V ~ 2.7V) or 3.3V (3.1V ~ 3.5V) Power Supply - VDDQ = 1.7V ~ 2.0V I/O Power Supply (VDD=1.8V) or 2.3V ~ 2.7V I/O Power Supply (VDD=2.5V) or 2.3V ~ 3.5V I/O Power Supply (VDD=3.3V) - Synchronous Operation - 2 Stage Pipelined operation with 4 Burst - On-Chip Address Counter - Self-Timed Write Cycle - On-Chip Address and Control Registers - Byte Writable Function - Global Write Enable Controls a full bus-width write - Power Down State via ZZ Signal - LBO Pin allows a choice of either a interleaved burst or a lin- ear burst - Three Chip Enables for simple depth expansion with No Data Contention only for TQFP ; 2cycle Enable, 1cycle Disable - Asynchronous Output Enable Control - ADSP, ADSC, ADV Burst Control Pins - TTL-Level Three-State Output - Operating in meical and industrial temperature range - 100-TQFP-1420A (Lead free package) - 165FBGA(11x15 ball array) with body size of 13mmx15mm. (Lead free package) General Description The S7A323630M and S7A321830M are 32,748,736-bit Synchronous Static Random Access Memory designed for high performance. It is organized as 1M(2M) words of 36(18) bits and integrates address and control registers, a 2-bit burst address counter and added some new functions for high performance applications; GW, BW, LBO, ZZ. Write cycles are internally self-timed and synchronous. Full bus-width write is done by GW, and each byte write is performed by the bination of WEx and BW when GW is high. And with CS1 high, ADSP is blocked to control signals....