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DS99R104 - (DS99R103 / DS99R104) DC-Balanced 24-Bit LVDS Serializer and Deserializer

Download the DS99R104 datasheet PDF (DS99R103 included). The manufacturer datasheet provides complete specifications, pinout details, electrical characteristics, and typical applications for (ds99r103 / ds99r104) dc-balanced 24-bit lvds serializer and deserializer.

Description

The DS99R103/104 Chipset translates a 24-bit parallel bus into a fully transparent data/control LVDS serial stream with embedded clock information.

Features

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  • 3 MHz.
  • 40 MHz clock embedded and DC-Balancing 24:1 and 1:24 data transmissions.
  • Capable to drive shielded twisted-pair cable.
  • User selectable clock edge for parallel data on both Transmitter and Receiver coupling interface with no external coding required Individual power-down controls for both Transmitter and Receiver Embedded clock CDR (clock and data recovery) on Receiver and no external source of reference clock needed All codes RDL (random da.

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Note: The manufacturer provides a single datasheet file (DS99R103_NationalSemiconductor.pdf) that lists specifications for multiple related part numbers.
Other Datasheets by National Semiconductor

Full PDF Text Transcription

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DS99R103/DS99R104 3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer April 2007 DS99R103/DS99R104 3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer General Description The DS99R103/104 Chipset translates a 24-bit parallel bus into a fully transparent data/control LVDS serial stream with embedded clock information. This single serial stream simplifies transferring a 24-bit bus over PCB traces and cable by eliminating the skew problems between parallel data and clock paths. It saves system cost by narrowing data paths that in turn reduce PCB layers, cable width, and connector size and pins. The DS99R103/104 incorporates LVDS signaling on the highspeed I/O. LVDS provides a low power and low noise environment for reliably transferring data over a serial transmission path.
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