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  ON Semiconductor Electronic Components Datasheet  

NB4L339 Datasheet

2.5 V / 3.3 V Differential 2:1 Clock IN to Differential LVPECL Clock Generator / Divider / Fan-Out Buffer

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NB4L339 pdf
NB4L339
2.5 V / 3.3 V Differential 2:1
Clock IN to Differential
LVPECL Clock Generator /
Divider / Fan-Out Buffer
MultiLevel Inputs w/ Internal Termination
Description
The NB4L339 is a multifunction Clock generator featuring a 2:1
Clock multiplexer front end and simultaneously outputs a selection of
four different divide ratios from its four divider blocks; ÷1/÷2/÷4/÷8.
One divide block has a choice of ÷1 or ÷ 2.
The output of each divider block is fannedout to two identical
differential LVPECL copies of the selected clock. All outputs provide
standard LVPECL voltage levels when externally terminated with a
50ohm resistor to VCC 2 V.
The differential Clock inputs incorporate internal 50W termination
resistors and will accept LVPECL, CML or LVDS logic levels.
The common Output Enable pin (EN) is synchronous so that the
internal dividers will only be enabled/disabled when the internal clock
is in the LOW state. This avoids any chance of generating a runt clock
pulse on the internal clock when the device is enabled/disabled as can
happen with an asynchronous control. An internal runt pulse could
lead to losing synchronization between the internal divider stages. The
internal enable flipflop is clocked on the falling edge of the input
clock. Therefore, all associated specification limits are referenced to
the negative edge of the clock input.
This device is housed in a 5x5 mm 32 pin QFN package.
Features
Maximum Input/Output Clock Frequency > 700 MHz
Low Skew LVPECL Outputs, 15 ps typical
1 ns Typical Propagation Delay
150 ps Typical Rise and Fall Times
0.15 ps Typical RMS Phase Jitter
0.5 ps Typical RMS Random Clock Period Jitter
LVPECL, CML or LVDS Input Compatible
Operating Range: VCC = 2.375 V to 3.6 V with VEE = 0 V
LVPECL Output Level; 750 mV PeaktoPeak, Typical
Internal 50W Input Termination Provided
Synchronous Output Enable/Disable
Asynchronous Master Reset
Functionally Compatible with Existing 2.5 V / 3.3 V LVEL, LVEP,
EP, and SG Devices
40°C to 85°C Ambient Operating Temperature
32Pin QFN, 5 mm x 5 mm
This is a PbFree Device
© Semiconductor Components Industries, LLC, 2012
September, 2012 Rev. 3
1
http://onsemi.com
MARKING
DIAGRAM
1 32
QFN32
MN SUFFIX
CASE 488AM
1
NB4L339
AWLYYWWG
G
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = PbFree Package
(Note: Microdot may be in either location)
Figure 1. Simplified Block Diagram
ORDERING INFORMATION
See detailed ordering and shipping information on page 11 of
this data sheet.
Publication Order Number:
NB4L339/D


  ON Semiconductor Electronic Components Datasheet  

NB4L339 Datasheet

2.5 V / 3.3 V Differential 2:1 Clock IN to Differential LVPECL Clock Generator / Divider / Fan-Out Buffer

No Preview Available !

NB4L339 pdf
NB4L339
DIVSEL
CLKSEL
A
÷1 / ÷2
R
A
QA0
QA0
QA1
QA1
foutA = 622.08 MHz
or 311.04 MHz
CLKA
VTA
CLKA
50W
50W
EXAMPLE: fin = 622.08 MHz
CLKB
VTB
CLKB
50W
50W
EN
MR
B
÷2
R
C
÷4
R
EN
D
÷8
R
Figure 2. Detailed Logic Diagram
QB0
B
QB0
QB1
foutB = 311.04 MHz
QB1
QC0
C
QC0
QC1
foutC = 155.52 MHz
QC1
QD0
D
QD0
QD1
foutD = 77.76 MHz
QD1
Table 1. Input Select Function Table
CLKSEL*
CLK Input Selected
0 CLKA
1 CLKB
Table 2. Divider Select Function Table
DIVSEL*
QA Divide
0 Divide by 1
1 Divide by 2
Table 3. Clock Enable/Disable Function Table
CLK Input
Low to High Transition
High to Low Transition
X (Don’t Care)
* Pin will default LOW when left OPEN.
EN* MR**
Function
0 H Divide Outputs Active
1 H Hold Q Outputs Inactive
X (Don’t Care)
L
Reset Q
** Pin will default HIGH when left OPEN.
VEE
CLKA
VTA
CLKA
CLKB
VTB
CLKB
VEE
32 31 30 29 28 27 26 25
1 24
2 Exposed Pad (EP) 23
3 22
4 21
NB4L339
5 20
6 19
7 18
89
10
17
11 12 13 14 15 16
QB0
QB0
QB1
QB1
QC0
QC0
QC1
QC1
Figure 3. Pinout QFN32 (Top View)
http://onsemi.com
2


Part Number NB4L339
Description 2.5 V / 3.3 V Differential 2:1 Clock IN to Differential LVPECL Clock Generator / Divider / Fan-Out Buffer
Maker ON Semiconductor
Total Page 12 Pages
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