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  ON Semiconductor Electronic Components Datasheet  

NB4L52 Datasheet

Differential Data/Clock D Flip-Flop

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NB4L52
2.5 V/3.3 V/5.0 V Differential
Data/Clock D Flip-Flop
with Reset
MultiLevel Inputs to LVPECL Translator
w/ Internal Termination
The NB4L52 is a differential Data and Clock D flipflop with a
differential asynchronous Reset. The differential inputs incorporate
internal 50 W termination resistors and will accept PECL, LVPECL,
LVCMOS, LVTTL, CML, or LVDS logic levels. When Clock
transitions from Low to High, Data will be transferred to the
differential LVPECL outputs. The differential Clock inputs allow the
NB4L52 to also be used as a negative edge triggered device. The
device is housed in a small 3x3 mm 16 pin QFN package.
Features
Maximum Input Clock Frequency > 4 GHz Typical
330 ps Typical Propagation Delay
145 ps Typical Rise and Fall Times
Differential LVPECL Outputs, 750 mV PeaktoPeak, Typical
Operating Range: VCC = 2.375 V to 5.5 V with VEE = 0 V
Internal Input Termination Resistors, 50 W
Functionally Compatible with Existing 2.5 V/3.3 V/5.0 V LVEL,
LVEP, EP, and SG Devices
40°C to +85°C Ambient Operating Temperature
These are PbFree Devices
http://onsemi.com
1
QFN16
MN SUFFIX
CASE 485G
MARKING DIAGRAM*
16
1
NB4L
52
ALYWG
G
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = PbFree Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
VTD
D
D
VTD
VTCLK
CLK
CLK
VTCLK
Data
Clock
Reset
Q
Q
© Semiconductor Components Industries, LLC, 2009
August, 2009 Rev. 3
VTR R R VTR
Figure 1. Logic Diagram
Table 1. TRUTH TABLE
R D CLK
Hx
x
LL
LH
Z
Z
Z = LOW to HIGH Transition
x = Don’t Care
Q
L
L
H
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
1 Publication Order Number:
NB4L52/D


  ON Semiconductor Electronic Components Datasheet  

NB4L52 Datasheet

Differential Data/Clock D Flip-Flop

No Preview Available !

NB4L52
VTR R
16 15
R VTR
14 13
VTD 1
D2
D3
NB4L52
12 VCC
11 Q
10 Q
VTD 4
9 VEE
56
VTCLK CLK
78
CLK VTCLK
Exposed Pad (EP)
Figure 2. Pinout (Top View)
Table 2. PIN DESCRIPTION
Pin Name
I/O
Description
1 VTD
Internal 50 W Termination Pin. (See Table 4)
2 D ECL, CML, LVCMOS, Noninverted Differential Input. (Note 1)
LVDS, LVTTL Input
3 D ECL, CML, LVCMOS, Inverted Differential Input. (Note 1)
LVDS, LVTTL Input
4 VTD
Internal 50 W Termination Pin. (See Table 4)
5 VTCLK
Internal 50 W Termination Pin. (See Table 4)
6 CLK ECL, CML, LVCMOS, Noninverted Differential Input. (Note 1)
LVDS, LVTTL Input
7 CLK ECL, CML, LVCMOS, Inverted Differential Input. (Note 1)
LVDS, LVTTL Input
8 VTCLK
9 VEE
10 Q
11 Q
12 VCC
13 VTR
14 R
ECL Output
ECL Output
LVECL, LVCMOS,
LVTTL Input
Internal 50 W Termination Pin. (See Table 4)
Negative Supply Voltage
Inverted Differential Output. Typically terminated with 50 W resistor to VCC 2.0 V.
Noninverted Differential Output. Typically terminated with 50 W resistor to VCC 2.0 V.
Positive Supply Voltage
Internal 50 W Termination Pin. (See Table 4)
Noninverted Differential Reset Input. (Note 1)
15 R
LVECL, LVCMOS,
LVTTL Input
Inverted Differential Reset Input. (Note 1)
16 VTR
Internal 50 W Termination Pin. (See Table 4)
EP
The Exposed Pad (EP) on the QFN16 package bottom is thermally connected to the die
for improved heat transfer out of package. The pad is not electrically connected to the die,
but is recommended to be electrically and thermally connected to VEE on the PC board.
1. In the differential configuration when the input termination pin (VTD, VTD, VTR, VTR, VTCLK, VTCLK) are connected to a common
termination voltage or left open, and if no signal is applied on D/D,CLK/CLK,R/R input then the device will be susceptible to selfoscillation.
http://onsemi.com
2


Part Number NB4L52
Description Differential Data/Clock D Flip-Flop
Maker ON Semiconductor
Total Page 8 Pages
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