RC32112A Datasheet | Renesas

Description The RC32112A is a fully integrated, low-power, highperformance network synchronizer, jitter attenuator and clock generator. The device supports JEDEC JESD204B/C for converter synchronization and Sync E for network-based synchronization. The RC32112A is ideal for providing reference clocks for high-speed serial links up to 28Gbps Ethernet in modular switch line cards and fabric cards in data center equipment, and for clocking data converters in small-cell wireless equipment. The device is a member of Renesas' high-performance Femto Clock family and radio clock family. Applications - Switches / routers - Network synchronization and jitter attenuation for 10 / 25 / 40 / 100 / 200 / 400 Gbps Ethernet PHYs in switch line cards - Clock generation for 10 /25 / 40 / 100 / 200 / 400 Gbps Ethernet PHYs in switch fabric cards - Small-cell wireless equipment for 4.5G and 5G - Medical imaging - Professional audio and video Product Options - 10 × 10 × 0.9 mm 72-VFQFPN package - 12 differential or 24 single-ended outputs Features - Can be configured as clock generator or jitter attenuator/synchronizer - Low power, less than 1.4W typical - Low jitter, less than 100 fs-RMS - pliant with ITU-T G.8262 and G.8262.1 option 1 and 2 for synchronous Ethernet Equipment Clock (EEC/e EEC) and G.8273.2 T-BC for synchronous Ethernet and PTP/IEEE 1588 tele boundary clock - PCIe Gen 1-6 CC, SRIS, and SRNS support - Jitter attenuation with programmable loop bandwidth from 0.1Hz to 12k Hz - Up to six fractional output dividers and 12 integer output dividers - Each fractional output divider can be slaved with DPLL or SYS-DPLL or free-run locked to APLL - DPLLs can be configured as DCO and each fractional output divider can be configured as NCO or DCO - bo bus allows frequency sharing between DPLLs, System DPLL, and each of the four fractional output dividers - LVCMOS, LVPECL, LVDS, HCSL, CML, SSTL, HSTL output modes supported with programmable output swing and mon mode voltage - JESD204B/C...