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TC58NVG5T2HTA00 - 32 GBIT (4G X 8 BIT) CMOS NAND E2PROM

General Description

The TC58NVG5T2HTA00 is a single 3.3 V 32 Gbit (40,478,441,472 bits) NAND Electrically Erasable and Programmable Read-Only Memory (NAND E2PROM) organized as (8192  1024) bytes  516 pages  1064 blocks.

Key Features

  • Organization Device capacity Register Page size Block size.
  • TC58NVG5T2HTA00 9216  516  1064  8 bits 9216  8 9216 bytes (4128K  516K) bytes Modes Read, Reset, Auto Page Program, Auto Block Erase, Status Read, Multi Page Program, Multi Page Read Mode control Serial input/output Command control Number of valid blocks Min 1028 blocks Max 1064 blocks Power supply VCC  2.7 V to 3.6 V Access time Cell array to register Serial Read Cycle Program/Erase time Auto Page Program Auto Block.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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TOSHIBA CONFIDENTIAL TENTATIVE TC58NVG5T2HTA00 TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 2 32 GBIT (4G  8 BIT) CMOS NAND E PROM (Triple-Level-Cell) DESCRIPTION The TC58NVG5T2HTA00 is a single 3.3 V 32 Gbit (40,478,441,472 bits) NAND Electrically Erasable and Programmable Read-Only Memory (NAND E2PROM) organized as (8192  1024) bytes  516 pages  1064 blocks. The device has one 9216-byte static registers which allow program and read data to be transferred between the register and the memory cell array in 9216-byte increments. The Erase operation is implemented in a single block unit (4128 Kbytes  516 Kbytes:9216 bytes  516 pages).