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XC95144XV Datasheet Preview

XC95144XV Datasheet

High-Performance CPLD

No Preview Available !

R
DS051 (v2.2) August 27, 2001
0
XC95144XV High-Performance
CPLD
0 1 Advance Product Specification
Features
• 144 macrocells with 3,200 usable gates
• Available in small footprint packages
- 100-pin TQFP (81 user I/O pins)
- 144-pin TQFP (117 user I/O pins)
- 144-pin CSP (117 user I/O pins)
• Optimized for high-performance 2.5V systems
- Low power operation
- Multi-voltage operation
• Advanced system features
- In-system programmable
- Two separate output banks
- Superior pin-locking and routability with
FastCONNECT II™ switch matrix
- Extra wide 54-input Function Blocks
- Up to 90 product-terms per macrocell with
individual product-term allocation
- Local clock inversion with three global and one
product-term clocks
- Individual output enable per output pin
- Input hysteresis on all user and boundary-scan pin
inputs
- Bus-hold ciruitry on all user pin inputs
- Full IEEE Standard 1149.1 boundary-scan (JTAG)
• Fast concurrent programming
• Slew rate control on individual outputs
• Enhanced data security features
• Excellent quality and reliability
- Endurance exceeding 10,000 program/erase
cycles
- 20 year data retention
- ESD protection exceeding 2,000V
Description
The XC95144XV is a 2.5V CPLD targeted for high-perfor-
mance, low-voltage applications in leading-edge communi-
cations and computing systems. It is comprised of eight
54V18 Function Blocks, providing 3,200 usable gates with
propagation delays of 4 ns.
Power Estimation
Power dissipation in CPLDs can vary substantially depend-
ing on the system frequency, design application and output
loading. To help reduce power dissipation, each macrocell
in a XC9500XV device may be configured for low-power
mode (from the default high-performance mode). In addi-
tion, unused product-terms and macrocells are automati-
cally deactivated by the software to further conserve power.
For a general estimate of ICC, the following equation may be
used:
ICC (mA) =
MCHP(0.36) + MCLP(0.23) + MC(0.005 mA/MHz) f
Where:
MCHP = Macrocells in high-performance (default) mode
MCLP = Macrocells in low-power mode
MC = Total number of macrocells used
f = Clock frequency (MHz)
This calculation is based on typical operating conditions
using a pattern of 16-bit up/down counters in each Function
Block with no output loading. The actual ICC value varies
with the design application and should be verified during
normal system operation.
Figure 1 shows the above estimation in a graphical form.
200
200 MHz
150
100 High PLeorfwormPaonwceer
50
120 MHz
0 40 80 120 160 200
Clock Frequency (MHz)
DS051_01_012501
Figure 1: Typical ICC vs. Frequency for XC95144XV
© 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS051 (v2.2) August 27, 2001
Advance Product Specification
www.xilinx.com
1-800-255-7778
1




Xilinx

XC95144XV Datasheet Preview

XC95144XV Datasheet

High-Performance CPLD

No Preview Available !

XC95144XV High-Performance CPLD
JTAG Port
3
1
JTAG
Controller
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O/GCK
I/O/GSR
I/O/GTS
3
1
4
I/O
Blocks
In-System Programming Controller
54
18
54
18
54
18
54
18
Function
Block 1
Macrocells
1 to 18
Function
Block 2
Macrocells
1 to 18
Function
Block 3
Macrocells
1 to 18
Function
Block 4
Macrocells
1 to 18
R
54
18
Function
Block 8
Macrocells
1 to 18
DS051_02_041000
Figure 2: XC95144XV Architecture
Function Block outputs (indicated by the bold line) drive the I/O Blocks directly.
2
www.xilinx.com
DS051 (v2.2) August 27, 2001
1-800-255-7778
Advance Product Specification


Part Number XC95144XV
Description High-Performance CPLD
Maker Xilinx
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XC95144XV Datasheet PDF





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