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CDCLVP110 - Low-Voltage 1:10 LVPECL/HSTL

General Description

The CDCLVP110 clock driver distributes one differential clock pair of either LVPECL or HSTL (selectable) input, (CLK0, CLK1) to ten pairs of differential LVPECL clock (Q0, Q9) outputs with minimum skew for clock distribution.

The CDCLVP110 can accept two clock sources into an input multiplexer.

Key Features

  • 1.
  • Distributes One Differential Clock Input Pair LVPECL/HSTL to 10 Differential LVPECL Clock Outputs.
  • Fully Compatible With LVECL/LVPECL/HSTL.
  • Single Supply Voltage Required, ±3.3-V or ±2.5-V Supply.
  • Selectable Clock Input Through CLK_SEL.
  • Low-Output Skew (Typ 15 ps) for Clock-Distribution.

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Other Datasheets by Texas Instruments

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CDCLVP1102 High-Performance Clock Buffer
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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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www.ti.com CDCLVP110 SCAS683D – JUNE 2002 – REVISED JANUARY 2011 Low-Voltage 1:10 LVPECL/HSTL With Selectable Input Clock Driver Check for Samples: CDCLVP110 FEATURES 1 • Distributes One Differential Clock Input Pair LVPECL/HSTL to 10 Differential LVPECL Clock Outputs • Fully Compatible With LVECL/LVPECL/HSTL • Single Supply Voltage Required, ±3.3-V or ±2.5-V Supply • Selectable Clock Input Through CLK_SEL • Low-Output Skew (Typ 15 ps) for Clock-Distribution Applications • VBB Reference Voltage Output for Single-Ended Clocking • Available in a 32-Pin LQFP Package • Frequency Range From DC to 3.