74AUP2G57 Datasheet PDF (Low-power dual PCB configurable multiple function gate)

74AUP2G57 - Low-power dual PCB configurable multiple function gate

Description

The 74AUP2G57 is a dual configurable multiple function gate with Schmitt-trigger inputs.

Each gate within the device can be configured as any of the following logic functions AND, OR, NAND, NOR, XNOR, inverter and buffer; using the 3-bit input.

All inputs can be connected directly to VCC or GND.

Features

Wide supply voltage range from 0.8 V to 3.6 V.
High noise immunity.
ESD protection:.
HBM JESD22-A114F exceeds 5000 V.
MM JESD22-A115-A exceeds 200 V.
CDM JESD22-C101E exceeds 1000 V.
Low static power consumption; ICC = 0.9 μA (maximum).
Latch-up performance exceeds 100 mA per JESD 78 Class II.
Inputs accept voltages up to 3.6 V.
Low noise overshoot and undershoot < 10% of VCC.
IOFF circuitry provi.

Datasheet Details

Part number	74AUP2G57
Manufacturer	nexperia
File Size	267.39 KB
Description	Low-power dual PCB configurable multiple function gate
Datasheet	74AUP2G57 Datasheet
Additional preview pages of the 74AUP2G57 datasheet.

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Full PDF Text Transcription

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74AUP2G57 Low-power dual PCB configurable multiple function gate Rev. 3 — 7 May 2021 Product data sheet 1. General description The 74AUP2G57 is a dual configurable multiple function gate with Schmitt-trigger inputs. Each gate within the device can be configured as any of the following logic functions AND, OR, NAND, NOR, XNOR, inverter and buffer; using the 3-bit input. All inputs can be connected directly to VCC or GND. This device ensures very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down. 2.

Published: Sep 11, 2017 |