Datasheet4U Logo Datasheet4U.com

AX1250ES

2A Sink/Source Bus Termination Regulator

AX1250ES Features

* include extremely low initial offset voltage, excellent load regulation, current limiting in bi-directions and on-chip thermal shut-down protection. The AX1250ES are available in the SOP-8L-EP (Exposed Pad) surface mount packages.  FEATURES Ideal for DDR-I, DDR-II and DDR-III VTT Applications Sink

AX1250ES General Description

The AX1250ES is a simple, cost-effective and high-speed linear regulator designed to generate termination voltage in double data rate (DDR) memory system to comply with the JEDEC SSTL_2 and SSTL_18 or other specific interfaces such as HSTL, SCSI-2 and SCSI-3 etc. devices requirements. The regulator .

AX1250ES Datasheet (653.14 KB)

Preview of AX1250ES PDF

Datasheet Details

Part number:

AX1250ES

Manufacturer:

AXElite

File Size:

653.14 KB

Description:

2a sink/source bus termination regulator.

📁 Related Datasheet

AX1250S 1.5A Sink/Source Bus Termination Regulator (AXElite)

AX125 Axcelerator Family FPGAs (Actel)

AX1201 1A Ultra Low Dropout Linear Regulator (AXElite)

AX1202 2A Ultra Low Dropout Linear Regulator (Axelite)

AX1203 3A Ultra Low Dropout Linear Regulator (AXElite)

AX1204 1A Ultra Low Dropout Linear Regulator (AXElite)

AX1205 2A Ultra Low Dropout Linear Regulator (AXElite)

AX1209 2A LDO Linear Regulator (AXElite)

AX120K Ceramic Composite Resistors (OHMITE)

AX1212 1.2V Output - 1A Low Dropout Linear Regulator (Axelite)

TAGS

AX1250ES Sink Source Bus Termination Regulator AXElite

Image Gallery

AX1250ES Datasheet Preview Page 2 AX1250ES Datasheet Preview Page 3

AX1250ES Distributor