AX1250ES - 2A Sink/Source Bus Termination Regulator

Product Overview

AXElite

Datasheet Details

Part number	AX1250ES
Manufacturer	AXElite
File Size	653.14 KB
Description	2A Sink/Source Bus Termination Regulator
Datasheet	AX1250ES Datasheet
Additional preview pages of the AX1250ES datasheet.

Product details

Description

The AX1250ES is a simple, cost-effective and high-speed linear regulator designed to generate termination voltage in double data rate (DDR) memory system to comply with the JEDEC SSTL_2 and SSTL_18 or other specific interfaces such as HSTL, SCSI-2 and SCSI-3 etc.

Features

include extremely low initial offset voltage, excellent load regulation, current limiting in bi-directions and on-chip thermal shut-down protection. The AX1250ES are available in the SOP-8L-EP (Exposed Pad) surface mount packages. .

📁 Similar Datasheet

AX125 - Axcelerator Family FPGAs (Actel)
AX1202 - 2A Ultra Low Dropout Linear Regulator (Axelite)
AX120K - Ceramic Composite Resistors (OHMITE)
AX1212 - 1.2V Output - 1A Low Dropout Linear Regulator (Axelite)
AX121K - Ceramic Composite Resistors (OHMITE)
AX12GK - Ceramic Composite Resistors (OHMITE)
AX1 - Full Wave Gas Filled Rectifying Valve (Philips)
AX1000 - Axcelerator Family FPGAs (Actel)

Other Datasheets by AXElite

AX1250S - 1.5A Sink/Source Bus Termination Regulator
AX1201 - 1A Ultra Low Dropout Linear Regulator
AX1203 - 3A Ultra Low Dropout Linear Regulator
AX1204 - 1A Ultra Low Dropout Linear Regulator
AX1205 - 2A Ultra Low Dropout Linear Regulator
AX1209 - 2A LDO Linear Regulator

Published: Jul 23, 2014 |