AX1250ES Datasheet (AXElite) - 2A Sink/Source Bus Termination Regulator

AX1250ES, 2A Sink/Source Bus Termination Regulator

The AX1250ES is a simple, cost-effective and high-speed linear regulator designed to generate termination voltage in double data rate (DDR) memory system to comply with the JEDEC SSTL_2 and SSTL_18 or other specific interfaces such as HSTL, SCSI-2 and SCSI-3 etc.

devices requirements.

The regulator

AX1250ES Features

* include extremely low initial offset voltage, excellent load regulation, current limiting in bi-directions and on-chip thermal shut-down protection. The AX1250ES are available in the SOP-8L-EP (Exposed Pad) surface mount packages.  FEATURES Ideal for DDR-I, DDR-II and DDR-III VTT Applications Sink