AS4C256K16E0 - 5V 256K x 16 CMOS DRAM

Alliance Semiconductor

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Datasheet Details

Part number	AS4C256K16E0
Manufacturer	Alliance Semiconductor
File Size	657.60 KB
Description	5V 256K x 16 CMOS DRAM
Datasheet	AS4C256K16E0_AllianceSemiconductor.pdf

AS4C256K16E0 Product details

Description

40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 GND I/O15 I/O14 I/O13 I/O12 GND I/O11 I/O10 I/O9 I/O8 NC LCAS UCAS OE A8 A7 A6 A5 A4 GND AS4C256K16E0 AS4C256K16E0 VCC I/O0 I/O1 I/O2 I/O3 VCC I/O4 I/O5 I/O6 I/O7 1 2 3 4 5 6 7 8 9 10 44 43 42 41 40 39 38 37 36 35 GND I/O15 I/O14 I/O13 I/O12 GND I/O11 I/O10 I/O9 I/O8 A0 to A8 Address inputs Row address strobe Output enable I/O0 to I/O15 OE UCAS LCAS WE Input/output Column address strobe, upper byte Column address strobe, l

Features

Organization: 262,144 words × 16 bits.
High speed - 30/35/50 ns RAS access time - 16/18/25 ns column address access time - 7/10/10/10 ns CAS access time.
Low power consumption - Active: 500 mW max (AS4C256K16E0-25) - Standby: 3.6 mW max, CMOS I/O (AS4C256K16E0-25).
EDO page mode.
Refresh - 512 refresh cycles, 8 ms refresh interval - RAS-only or CAS-before-RAS refresh or self-refresh - Self-refresh option is available for new generation device only. C.

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Other Datasheets by Alliance Semiconductor

AS4C256K16FO - 5V 256K x 16 CMOS DRAM
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AS4C256M16D3B-12BCN - Double-data-rate architecture
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AS4C256M16D3LB-12BAN - 4Gb DRAM

Published: Mar 5, 2006 |