AS4C4M4E1 - 4M x 4 CMOS DRAM

Alliance Semiconductor

AS4C4M4E1 Datasheet Preview — Preview of AS4C4M4E1 PDF

Datasheet Details

Part number	AS4C4M4E1
Manufacturer	Alliance Semiconductor
File Size	358.09 KB
Description	4M x 4 CMOS DRAM
Datasheet	AS4C4M4E1_AllianceSemiconductor.pdf

AS4C4M4E1 Product details

Description

Address inputs Row address strobe Column address strobe Write enable Input/output Output enable Power Ground A0 to A10 t e U 4 .c m o I/O0 to I/O3 GND Symbol tRAC tCAA tCAC tOEA tRC tPC ICC1 ICC5 AS4C4M4E1-50 50 25 12 13 85 25 135 2.0 AS4C4M4E1-60 60 30 15 15 100 30 120 Unit Alliance Semiconductor w w w 2.0 .D a ta e h S et 4U ns ns ns ns ns ns .m o c mA mA P.1 of 14 Copyright © Alliance Semiconductor.All rights reserved.AS4C4M4E1 ® Functional description The AS4C

Features

Organization: 4,194,304 words × 4 bits.
High speed - 50/60 ns RAS access time - 25/30 ns column address access time - 12/15 ns CAS access time.
TTL-compatible, three-state I/O.
JEDEC standard package - 300 mil, 24/26-pin SOJ - 300 mil, 24/26-pin TSOP.
Low power consumption - Active: 908 mW max - Standby: 5.5 mW max, CMOS I/O.
Extended data out.
Refresh - 2048 refresh cycles, 32 ms refresh interval for AS4C4M4E1 - RAS-only or CAS-.

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Other Datasheets by Alliance Semiconductor

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Published: Mar 5, 2006 |