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ADP7112 CMOS LDO Linear Regulator

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Description

Data Sheet .
The ADP7112 is a CMOS, low dropout (LDO) linear regulator that operates from 2.

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Features

* Low noise: 11 μV rms independent of fixed output voltage PSRR of 88 dB at 10 kHz, 68 dB at 100 kHz, 50 dB at 1 MHz, VOUT = 5 V, VIN = 7 V Input voltage range: 2.7 V to 20 V Maximum output current: 200 mA Initial accuracy: ±0.8% Accuracy over line, load, and temperature ±1.8%, TJ =
* 40°C to +

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