CY7C1161KV18 Datasheet - Cypress Semiconductor

CY7C1161KV18 - 18-Mbit QDR II SRAM Four-Word Burst Architecture

The CY7C1161KV18, CY7C1176KV18, CY7C1163KV18, and CY7C1165KV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port ha.

CY7C1161KV18 Features

* Configurations With Read Cycle Latency of 2.5 cycles: CY7C1161KV18

* 2 M x 8 CY7C1176KV18

* 2 M x 9 CY7C1163KV18

* 1 M x 18 CY7C1165KV18

* 512 K x 36 Separate independent read and write data ports

* Supports concurrent transactions 550-MHz clock for high b

CY7C1161KV18_CypressSemiconductor.pdf