CY7C1314KV18, CY7C1312KV18 Datasheet - Cypress Semiconductor

CY7C1314KV18 18-Mbit QDR II SRAM Two-Word Burst Architecture

The CY7C1312KV18, and CY7C1314KV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II architecture. QDR II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicated data outputs to support read operations and the wr.

CY7C1314KV18 Features

* Separate independent read and write data ports

* Supports concurrent transactions

* 333 MHz clock for high bandwidth

* Two-word burst on all accesses

* Double-data rate (DDR) interfaces on both read and write ports (data transferred at 666 MHz) at 333 MHz

* Two input clocks

CY7C1312KV18-CypressSemiconductor.pdf

CY7C1314KV18 Datasheet Preview — This datasheet PDF includes multiple part numbers: CY7C1314KV18, CY7C1312KV18. Please refer to the document for exact specifications by model.

Datasheet Details

Part number:

CY7C1314KV18, CY7C1312KV18

Manufacturer:

Cypress Semiconductor

File Size:

790.78 KB

Description:

18-mbit qdr ii sram two-word burst architecture.

Note:

This datasheet PDF includes multiple part numbers: CY7C1314KV18, CY7C1312KV18.
Please refer to the document for exact specifications by model.

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TAGS

CY7C1314KV18 CY7C1312KV18 18-Mbit QDR SRAM Two-Word Burst Architecture Cypress Semiconductor

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