CY7C1429AV18 - 36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture

Product Overview

Cypress Semiconductor

Datasheet Details

Part number	CY7C1429AV18
Manufacturer	Cypress Semiconductor
File Size	502.12 KB
Description	36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
Datasheet	CY7C1429AV18 Datasheet
Note	This datasheet PDF includes multiple part numbers: CY7C1429AV18, CY7C1422AV18. Please refer to the document for exact specifications by model.
Additional preview pages of the CY7C1429AV18 datasheet.

Product details

Description

The CY7C1422V18, CY7C1429AV18, CY7C1423V18, CY7C1424V18 are 1.8V Synchronous Pipelined SRAMs equipped with DDR-II SIO (Double Data Rate Separate I/O) architecture.

Features

36-Mbit density (4M x 8, 4M x 9, 2M x 18, 1M x 36).
300-MHz clock for high bandwidth.
2-Word burst for reducing address bus frequency.
Double Data Rate (DDR) interfaces (data transferred at 600 MHz) @ 300 MHz.
Two input clocks (K and K) for precise DDR timing.
SRAM uses rising edges only.
Two input clocks for output data (C and C) to minimize clock-skew and flight-time mismatches.
Echo clocks (CQ and CQ) simplify data captu.

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Published: Apr 15, 2011 |