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CY7C331

Asynchronous Registered EPLD

CY7C331 Features

* Twelve I/O macrocells each having:

* One state flip-flop with an XOR sum-of-products input

* One feedback flip-flop with input coming from the I/O pin

* Independent (product term) set, reset, and clock inputs on all registers

* Asynchronous bypass capability on

CY7C331 General Description

The CY7C331 is the most versatile PLD available for asynchronous designs. Central resources include twelve full D-type flip-flops with separate set, reset, and clock capability. For increased utility, XOR gates are provided at the D-inputs and the product term allocation per flip-flop is variably distri.

CY7C331 Datasheet (361.24 KB)

Preview of CY7C331 PDF

Datasheet Details

Part number:

CY7C331

Manufacturer:

Cypress Semiconductor

File Size:

361.24 KB

Description:

Asynchronous registered epld.

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TAGS

CY7C331 Asynchronous Registered EPLD Cypress Semiconductor

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