CY7C331 - Asynchronous Registered EPLD
The CY7C331 is the most versatile PLD available for asynchronous designs.
Central resources include twelve full D-type flip-flops with separate set, reset, and clock capability.
For increased utility, XOR gates are provided at the D-inputs and the product term allocation per flip-flop is variably distri
CY7C331 Features
* Twelve I/O macrocells each having:
* One state flip-flop with an XOR sum-of-products input
* One feedback flip-flop with input coming from the I/O pin
* Independent (product term) set, reset, and clock inputs on all registers
* Asynchronous bypass capability on
