* z JEDEC standard 3.3V power supply z LVTTL compatible with multiplexed address z Dual banks operation z MRS cycle with address key programs - CAS Latency (2 & 3 ) www.DataSheet4U-.comBurst Length (1, 2, 4, 8 & full page) - Burst Type (Sequential & Interleave) z All inputs are sampled at the positive
M12L32162A-7BG Datasheet (755.29 KB)
M12L32162A-7BG
ESMT
755.29 KB
1m x 16bit x 2banks synchronous dram.
ESMT Preliminary Revision History Revision 0.1 (Aug. 11 2006) - Original Revision 0.2 (Mar. 20 2007) - Add BGA package Revision 0.3 (Apr. 27 2007) -.
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