Datasheet4U Logo Datasheet4U.com

M12L32321A-6BG2G

512K x 32Bit x 2Banks Synchronous DRAM

M12L32321A-6BG2G Datasheet (526.90 KB)

Preview of M12L32321A-6BG2G PDF Datasheet

Datasheet Details

Part number:

M12L32321A-6BG2G

Manufacturer:

ESMT

File Size:

526.90 KB

Description:

512k x 32bit x 2banks synchronous dram

M12L32321A-6BG2G Features

* JEDEC standard 3.3V ± 0.3V power supply

* LVTTL compatible with multiplexed address

* Dual banks operation

* MRS cycle with address key programs - CAS Latency (2 & 3 ) - Burst Length (1, 2, 4, 8 & full page) - Burst Type (Sequential & Interleave)

* All inputs are sampled at the

M12L32321A-6BG2G General Description

The M12L32321A is 33,554,432 bits synchronous high data rate Dynamic RAM organized as 2 x 524,288 words by 32 bits, fabricated with high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range.

📁 Related Datasheet

M12L32321A-5BG2G - 512K x 32Bit x 2Banks Synchronous DRAM (ESMT)
ESMT SDRAM M12L32321A (2G) 512K x 32Bit x 2Banks Synchronous DRAM FEATURES  JEDEC standard 3.3V ± 0.3V power supply  LVTTL patible with multipl.

M12L32321A-7BG2G - 512K x 32Bit x 2Banks Synchronous DRAM (ESMT)
ESMT SDRAM M12L32321A (2G) 512K x 32Bit x 2Banks Synchronous DRAM FEATURES  JEDEC standard 3.3V ± 0.3V power supply  LVTTL patible with multipl.

M12L32162A-7BG - 1M x 16Bit x 2Banks Synchronous DRAM (ESMT)
ESMT Preliminary Revision History Revision 0.1 (Aug. 11 2006) - Original Revision 0.2 (Mar. 20 2007) - Add BGA package Revision 0.3 (Apr. 27 2007) -.

M12L32162A-7TG - 1M x 16Bit x 2Banks Synchronous DRAM (ESMT)
ESMT Preliminary Revision History Revision 0.1 (Aug. 11 2006) - Original Revision 0.2 (Mar. 20 2007) - Add BGA package Revision 0.3 (Apr. 27 2007) -.

M12L128168A-5BG - 2M x 16 Bit x 4 Banks Synchronous DRAM (ESMT)
ESMT SDRAM FEATURES y JEDEC standard 3.3V power supply y LVTTL patible with multiplexed address y Four banks operation y MRS cycle with address key.

M12L128168A-5BG2N - 2M x 16 Bit x 4 Banks Synchronous DRAM (ESMT)
ESMT SDRAM FEATURES y JEDEC standard 3.3V power supply y LVTTL patible with multiplexed address y Four banks operation y MRS cycle with address key.

TAGS

M12L32321A-6BG2G 512K 32Bit 2Banks Synchronous DRAM ESMT

Image Gallery

M12L32321A-6BG2G Datasheet Preview Page 2 M12L32321A-6BG2G Datasheet Preview Page 3

M12L32321A-6BG2G Distributor