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M15F2G16128A-EFBG2LS

DDR3 SDRAM

M15F2G16128A-EFBG2LS Features

* and all of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and CK falling). All I/Os are synchronized with a single ended DQS or differential DQS pair in a source synchrono

M15F2G16128A-EFBG2LS General Description

The 2Gb Double-Data-Rate-3 (DDR3) DRAM is double data rate architecture to achieve high-speed operation. It is internally configured as an eight bank DRAMs. The 2Gb chip is organized as 16Mbit x 16 I/Os x 8 bank devices. These synchronous devices achieve high speed double-data-rate transfer rates of.

M15F2G16128A-EFBG2LS Datasheet (4.19 MB)

Preview of M15F2G16128A-EFBG2LS PDF

Datasheet Details

Part number:

M15F2G16128A-EFBG2LS

Manufacturer:

ESMT

File Size:

4.19 MB

Description:

Ddr3 sdram.

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M15F2G16128A-EFBG2LS DDR3 SDRAM ESMT

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