M15F2G16128A-BDBG2F Datasheet, Sdram, ESMT

M15F2G16128A-BDBG2F Features

• Sdram and all of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK risin

PDF File Details

Part number:

M15F2G16128A-BDBG2F

Manufacturer:

ESMT

File Size:

1.79MB

Download:

📄 Datasheet

Description:

16m x 16 bit x 8 banks ddr iii sdram. The 2Gb Double-Data-Rate-3 (DDR3) DRAM is double data rate architecture to achieve high-speed operation. It is internally configured

TAGS

M15F2G16128A-BDBG2F

ESMT

📁 Related Datasheet

M15F2G16128A-BDBIG2B - 16M x 16 Bit x 8 Banks DDR3 SDRAM (ESMT)
ESMT DDR3 SDRAM Feature z Interface and Power Supply „ SSTL_15: VDD/VDDQ = 1.5V(±0.075V) z JEDEC DDR3 Compliant „ 8n Prefetch Architecture „ Different.

M15F2G16128A-DEBG2L - DDR3 SDRAM (ESMT)
ESMT DR3 SDRAM Feature  Interface and Power Supply ˗ SSTL_15: VDD/VDDQ = 1.5V(±0.075V)  JEDEC DDR3 Compliant ˗ 8n Prefetch Architecture ˗ Differenti.

M15F2G16128A-DEBG2L - 16M x 16 Bit x 8 Banks DDR3 SDRAM (ESMT)
ESMT DR3 SDRAM Feature  Interface and Power Supply ˗ SSTL_15: VDD/VDDQ = 1.5V(±0.075V)  JEDEC DDR3 Compliant ˗ 8n Prefetch Architecture ˗ Differenti.

M15F2G16128A-DEBG2LS - DDR3 SDRAM (ESMT)
ESMT DR3 SDRAM Feature  Interface and Power Supply ˗ SSTL_15: VDD/VDDQ = 1.5V(±0.075V)  JEDEC DDR3 Compliant ˗ 8n Prefetch Architecture ˗ Differenti.

M15F2G16128A-DEBG2LS - 16M x 16 Bit x 8 Banks DDR3 SDRAM (ESMT)
ESMT DR3 SDRAM Feature  Interface and Power Supply ˗ SSTL_15: VDD/VDDQ = 1.5V(±0.075V)  JEDEC DDR3 Compliant ˗ 8n Prefetch Architecture ˗ Differenti.

M15F2G16128A-DEBIG2B - 16M x 16 Bit x 8 Banks DDR3 SDRAM (ESMT)
ESMT DDR3 SDRAM Feature z Interface and Power Supply „ SSTL_15: VDD/VDDQ = 1.5V(±0.075V) z JEDEC DDR3 Compliant „ 8n Prefetch Architecture „ Different.

M15F2G16128A-EFBG2L - DDR3 SDRAM (ESMT)
ESMT DR3 SDRAM Feature  Interface and Power Supply ˗ SSTL_15: VDD/VDDQ = 1.5V(±0.075V)  JEDEC DDR3 Compliant ˗ 8n Prefetch Architecture ˗ Differenti.

M15F2G16128A-EFBG2L - 16M x 16 Bit x 8 Banks DDR3 SDRAM (ESMT)
ESMT DR3 SDRAM Feature  Interface and Power Supply ˗ SSTL_15: VDD/VDDQ = 1.5V(±0.075V)  JEDEC DDR3 Compliant ˗ 8n Prefetch Architecture ˗ Differenti.

M15F2G16128A-EFBG2LS - DDR3 SDRAM (ESMT)
ESMT DR3 SDRAM Feature  Interface and Power Supply ˗ SSTL_15: VDD/VDDQ = 1.5V(±0.075V)  JEDEC DDR3 Compliant ˗ 8n Prefetch Architecture ˗ Differenti.

M15F2G16128A-EFBG2LS - 16M x 16 Bit x 8 Banks DDR3 SDRAM (ESMT)
ESMT DR3 SDRAM Feature  Interface and Power Supply ˗ SSTL_15: VDD/VDDQ = 1.5V(±0.075V)  JEDEC DDR3 Compliant ˗ 8n Prefetch Architecture ˗ Differenti.