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M15F2G16128A-DEBG2LS, M15F2G16128A Datasheet - ESMT

M15F2G16128A-DEBG2LS DDR3 SDRAM

The 2Gb Double-Data-Rate-3 (DDR3) DRAM is double data rate architecture to achieve high-speed operation. It is internally configured as an eight bank DRAMs. The 2Gb chip is organized as 16Mbit x 16 I/Os x 8 bank devices. These synchronous devices achieve high speed double-data-rate transfer rates of.

M15F2G16128A-DEBG2LS Features

* and all of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and CK falling). All I/Os are synchronized with a single ended DQS or differential DQS pair in a source synchrono

M15F2G16128A-ESMT.pdf

This datasheet PDF includes multiple part numbers: M15F2G16128A-DEBG2LS, M15F2G16128A. Please refer to the document for exact specifications by model.
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Datasheet Details

Part number:

M15F2G16128A-DEBG2LS, M15F2G16128A

Manufacturer:

ESMT

File Size:

4.19 MB

Description:

Ddr3 sdram.

Note:

This datasheet PDF includes multiple part numbers: M15F2G16128A-DEBG2LS, M15F2G16128A.
Please refer to the document for exact specifications by model.

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TAGS

M15F2G16128A-DEBG2LS M15F2G16128A DDR3 SDRAM ESMT

M15F2G16128A-DEBG2LS Distributor