M15F2G16128A-DEBIG2B - 16M x 16 Bit x 8 Banks DDR3 SDRAM
The 2Gb Double-Data-Rate-3 (DDR3) DRAM is double data rate architecture to achieve high-speed operation.
It is internally configured as an eight bank DRAMs.
The 2Gb chip is organized as 16Mbit x 16 I/Os x 8 bank devices.
These synchronous devices achieve high speed double-data-rate transfer rates of
M15F2G16128A-DEBIG2B Features
* and all of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and CK ใfalling). All I/Os are synchronized with a single ended DQS or differential DQS pair in a source synchron
