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M15T2G8256A Datasheet - ESMT

M15T2G8256A - DDR3 SDRAM

The 2Gb Double-Data-Rate-3(L) (DDR3(L)) DRAM is double data rate architecture to achieve high-speed operation.

It is internally configured as an eight bank DRAMs.

The 2Gb chip is organized as 32Mbit x 8 I/Os x 8 bank devices.

These synchronous devices achieve high speed double-data-rate transfer rat

M15T2G8256A Features

* and all of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and CK falling). All I/Os are synchronized with a single ended DQS or differential DQS pair in a source synchrono

M15T2G8256A-ESMT.pdf

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Datasheet Details

Part number:

M15T2G8256A

Manufacturer:

ESMT

File Size:

3.29 MB

Description:

Ddr3 sdram.

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