M15T2G8256A Datasheet - ESMT

DDR3 SDRAM

M15T2G8256A Features

* and all of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and CK falling). All I/Os are synchronized with a single ended DQS or differential DQS pair in a source synchrono

M15T2G8256A General Description

The 2Gb Double-Data-Rate-3(L) (DDR3(L)) DRAM is double data rate architecture to achieve high-speed operation. It is internally configured as an eight bank DRAMs. The 2Gb chip is organized as 32Mbit x 8 I/Os x 8 bank devices. These synchronous devices achieve high speed double-data-rate transfer rat.

M15T2G8256A Datasheet (3.29 MB)