74LS107 Datasheet - ETC

Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops

74LS107 General Description

This device contains two independent negative-edge-triggered J-K flip-flops with complementary outputs The J and K data is processed by the flip-flops on the falling edge of the clock pulse The clock triggering occurs at a voltage level and is not directly related to the transition time of the negat.

74LS107 Datasheet (143.69 KB)

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Part number:

74LS107

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ETC

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143.69 KB

Description:

Dual negative-edge-triggered master-slave j-k flip-flops.
DM54LS107A DM74LS107A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs June 1989 DM54LS107A DM74LS107A .

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74LS107 Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops ETC

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74LS107 General Description

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