74LS11
Fairchild Semiconductor
46.02kb
Triple 3-input and gate. This device contains three independent gates each of which performs the logic AND function. Ordering Code: Order Number DM74LS11M DM
📁 Related Datasheet
74LS10 - TRIPLE 3-INPUT NAND GATE
(ON Semiconductor)
SN54/74LS10 TRIPLE 3-INPUT NAND GATE
TRIPLE 3-INPUT NAND GATE
VCC 14 13 12 11 10 9 8
LOW POWER SCHOTTKY
1
2
3
4
5
6
7 GND
14 1
J SUFFIX CERA.
74LS10 - Triple 3-Input NAND Gate
(Fairchild Semiconductor)
DM74LS10 Triple 3-Input NAND Gate
August 1986 Revised March 2000
DM74LS10 Triple 3-Input NAND Gate
General Description
This device contains three in.
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DM54LS107A DM74LS107A .
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..
..
..
..
.
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..
SN74LS109A Dual JK Positive Edge-Triggered Flip-Flop
The SN74LS109A consists of two high speed pletely independent transition .
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PACKAGE OPTION ADDENDUM
4-Dec-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package Eco Plan
(1)
Drawi.
74LS112 - Dual J-K Negative-edge-triggered Flip-Flops
(Hitachi Semiconductor)
19.20 20.00 Max 16 9 7.40 Max 6.30
Unit: mm
1 1.3
1.11 Max
8
0.51 Min
2.54 Min 5.06 Max
7.62
2.54 ± 0.25
0.48 ± 0.10
0.25 – 0.05 0° – 15°
Hit.
74LS112A - DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP
(Motorola)
DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP
The SN54 / 74LS112A dual JK flip-flop features individual J, K, clock, and asynchronous set and clear inputs.
74LS112A - Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop
(Fairchild Semiconductor)
DM74LS112A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs
August 1986 Revised March 2000
DM74.
74LS114A - DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP
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SN54/74LS114A DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP
The SN54/ 74LS114A offers mon clock and mon clear inputs and individual J, K, and set in.
