74LS112A Features
* individual J, K, clock, and asynchronous set and clear inputs to each flip-flop. When the clock goes HIGH, the inputs are enabled and data will be accepted. The logic level of the J and K inputs may be allowed to change when the clock pulse is HIGH and the bistable will perform according to the trut
Datasheet Details
74LS112A, 74LS112
Motorola
147.34 KB
Dual jk negative edge-triggered flip-flop.
This datasheet PDF includes multiple part numbers: 74LS112A, 74LS112.
Please refer to the document for exact specifications by model.
74LS112A Distributor
📁 Related Datasheet
74LS112 Dual J-K Negative-edge-triggered Flip-Flops (Hitachi Semiconductor)
74LS112A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop (Fairchild Semiconductor)
74LS11 Triple 3-Input AND Gate (Fairchild Semiconductor)
74LS114A DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP (Motorola)
74LS10 TRIPLE 3-INPUT NAND GATE (ON Semiconductor)
74LS10 Triple 3-Input NAND Gate (Fairchild Semiconductor)
74LS107 Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops (ETC)
74LS109 Dual J-K Flip-Flop (Agere Systems)
