74LS112A Features
* individual J, K, clock, and asynchronous set and clear inputs to each flip-flop. When the clock goes HIGH, the inputs are enabled and data will be accepted. The logic level of the J and K inputs may be allowed to change when the clock pulse is HIGH and the bistable will perform according to the trut
Datasheet Details
74LS112A, 74LS112
Motorola
147.34 KB
Dual jk negative edge-triggered flip-flop.
This datasheet PDF includes multiple part numbers: 74LS112A, 74LS112.
Please refer to the document for exact specifications by model.
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