SLGSSTU32864E Datasheet (ETC) - DDR2 Configurable Registered Buffer

SLGSSTU32864E, DDR2 Configurable Registered Buffer

The SLGSSTU32864 is a configurable registered buffer designed for 1.7V to 1.9V VDD operating range.

When C1 input pin is low, the SLGSSTU32864 is 1:1 25-bit configuration.

When C1 input pin is high, the SLGSSTU32864 is 1:2 14-bit configuration.

Additionally, C0 input pin controls the 1:2 pinout as r

SLGSSTU32864E Features

* Compatible with JEDEC standard SSTU32864

* Differential Clock inputs

* SSTL_18 Clock and data input signaling

* Output circuitry minimizes effects of SSO and unterminated lines

* LVCMOS input levels on control and RESET pins

* 1.7V-1.9V Supply volta