SLGSSTVF16859V - DDR 13 to 26 Bit Registered Buffer
The 14-bit SLGSSTVF16859 is a registered buffer designed for 2.3V to 2.7V VDD operating range.
Inputs are SSTL_2 levels, except for the LVCMOS RESET input.
Data propagation from D to Q is controlled by the differential clock (CLK/CLK) and a control signal (RESET).
The rising edge of CLK (crossing wi
SLGSSTVF16859V Features
* Compatible with JEDEC standard SSTV16859
* Differential Clock inputs
* SSTL_2 data input signaling
* Supports SSTL_2 class I output specifications
* Output circuitry minimizes effects of SSO and unterminated lines www.DataSheet4U.com
* LVCMOS input
