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74LS112A, 74LS112 Datasheet - Fairchild Semiconductor

74LS112A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop

This device contains two independent negative-edge-triggered J-K flip-flops with complementary outputs. The J and K data is processed by the flip-flop on the falling edge of the clock pulse. The clock triggering occurs at a voltage level and is not directly related to the transition time of the fall.

74LS112_FairchildSemiconductor.pdf

This datasheet PDF includes multiple part numbers: 74LS112A, 74LS112. Please refer to the document for exact specifications by model.
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Datasheet Details

Part number:

74LS112A, 74LS112

Manufacturer:

Fairchild Semiconductor

File Size:

52.01 KB

Description:

Dual negative-edge-triggered master-slave j-k flip-flop.

Note:

This datasheet PDF includes multiple part numbers: 74LS112A, 74LS112.
Please refer to the document for exact specifications by model.

74LS112A Distributor

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74LS112A 74LS112 Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop Fairchild Semiconductor