74LS112A Datasheet - Fairchild Semiconductor

Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop

74LS112A General Description

This device contains two independent negative-edge-triggered J-K flip-flops with complementary outputs. The J and K data is processed by the flip-flop on the falling edge of the clock pulse. The clock triggering occurs at a voltage level and is not directly related to the transition time of the fall.

74LS112A Datasheet (52.01 KB)

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Part number:

74LS112A

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Fairchild Semiconductor

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52.01 KB

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Dual negative-edge-triggered master-slave j-k flip-flop.
DM74LS112A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs August 1986 Revised March 2000 DM74.

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74LS112A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop Fairchild Semiconductor

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74LS112A General Description

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