FDV302P Datasheet - Fairchild Semiconductor

FDV302P Digital FET/ P-Channel

This P-Channel logic level enhancement mode field effect transistor is produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. This device has been designed especially for low voltage applicati.

FDV302P Features

* -25 V, -0.12 A continuous, -0.5 A Peak. RDS(ON) = 13 Ω @ VGS= -2.7 V RDS(ON) = 10 Ω @ VGS = -4.5 V. Very low level gate drive requirements allowing direct operation in 3V circuits. VGS(th) < 1.5V. Gate-Source Zener for ESD ruggedness. >6kV Human Body Model Compact industry standard SOT-23 surface mo

FDV302P_FairchildSemiconductor.pdf