NDP6030PL Datasheet - Fairchild

NDP6030PL P-Channel Logic Level Enhancement Mode Field Effect Transistor

These P-Channel logic level enhancement mode power field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. These devices are particularly suited for low voltage app.

NDP6030PL Features

* -30 A, -30 V. RDS(ON) = 0.042 Ω @ VGS= -4.5 V RDS(ON) = 0.025 Ω @ VGS= -10 V. Critical DC electrical parameters specified at elevated temperature. Rugged internal source-drain diode can eliminate the need for an external Zener diode transient suppressor. High density cell design for extremely low RD

NDP6030PL Datasheet (56.60 KB)

NDP6030PL Datasheet Preview — Preview of NDP6030PL PDF

Datasheet Details

Part number:

NDP6030PL

Manufacturer:

Fairchild

File Size:

56.60 KB

Description:

P-channel logic level enhancement mode field effect transistor.

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NDP6030PL P-Channel Logic Level Enhancement Mode Field Effect Transistor Fairchild

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