H57V2622GMR-75X, H57V2622GMR Datasheet (Hynix Semiconductor)

H57V2622GMR-75X, H57V2622GMR, 256Mb Dual Die Synchronous DRAM

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Rev 1.0 / Oct.

2009 1 www.DataSheet4U.com 111 Synchronous DRAM Memory 256Mbit H57V2622GMR Series Document Title 256Mbit (8M x32) Synchronous DRAM Rev

H57V2622GMR-75X Features

* Standard SDRAM Protocol Uses 2pcs of 128Mb Monolithic Die Power Supply Voltage : VDD = 3.3V, VDDQ = 3.3V All device pins are compatible with LVTTL interface 4096 Refresh cycles / 64ms Programmable CAS latency of 2 or 3 Programmable Burst Length and Burst Type Operating Temp. - Commercial Temp