* VDD, VDDQ = 2.5V +/- 0.2V All inputs and outputs are compatible with SSTL_2 interface Fully differential clock inputs (CK, /CK) operation Double data rate interface Source synchronous - data transaction aligned to bidirectional da
HY5DU121622ALT Datasheet (427.98 KB)
HY5DU121622ALT
Hynix Semiconductor
427.98 KB
512mb ddr sdram.
www.DataSheet4U.com HY5DU12422A(L)T HY5DU12822A(L)T HY5DU121622A(L)T 512Mb DDR SDRAM HY5DU12422A(L)T HY5DU12822A(L)T HY5DU121622A(L)T This document.
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