Description
HY5DU12422B(L)TP HY5DU12822B(L)TP HY5DU121622B(L)TP 512Mb DDR SDRAM HY5DU12422B(L)TP HY5DU12822B(L)TP HY5DU121622B(L)TP This document is a general p.
Features
* VDD, VDDQ = 2.5V +/- 0.2V All inputs and outputs are compatible with SSTL_2 interface Fully differential clock inputs (CK, /CK) operation Double data rate interface Source synchronous - data transaction aligned to bidirectional daApplications
* which requires large memory density and high bandwidth. This Hynix 512Mb DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data, Data strHY5DU121622B Distributors
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