HY5DU121622C - 512 Mb DDR SDRAM
and is subject to change without notice.
Hynix Semiconductor does not assume any responsibility for use of circuits described.
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Rev.
1.0 / Mar.
2005 1 HY5DU12822C(L)TP HY5DU121622C(L)TP 1HY5DU12422C(L)TP Revision History Revision No.
1.0 First Version Release Histor
HY5DU121622C Features
* VDD, VDDQ = 2.5V ± 0.2V for DDR200, 266, 333 VDD, VDDQ = 2.6V ± 0.1V for DDR400 All inputs and outputs are compatible with SSTL_2 interface Fully differential clock inputs (CK, /CK) operation Double data rate interface Source sync
