Description
HY5DU28422A(L)T HY5DU28822A(L)T HY5DU281622A(L)T 3rd 128M DDR SDRAM HY5DU28422A(L)T HY5DU28822A(L)T HY5DU281622A(L)T This document is a general prod.
Features
* VDD, VDDQ = 2.5V +/- 0.2V All inputs and outputs are compatible with SSTL_2 interface Fully differential clock inputs (CK, /CK) operation Double data rate interface Source synchronous - data transaction aligned to bidirectional data strobeApplications
* which requires large memory density and high bandwidth. The Hynix 128Mb DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data, Data stroHY5DU28822LT Distributors
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