* VDD, VDDQ = 2.6V +/- 0.1V All inputs and outputs are compatible with SSTL_2 interface Fully differential clock inputs (CK, /CK) operation Double data rate interface Source synchronous - data transaction aligned to bidirectional da
HY5DU28822LT Datasheet (560.43 KB)
HY5DU28822LT
Hynix Semiconductor
560.43 KB
(hy5du28xx22d(l)t) 128mb-s ddr sdram.
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HY5DU28422D(L)T HY5DU28822D(L)T HY5DU281622D(L)T
128Mb-S DDR SDRAM
HY5DU28422D(L)T HY5DU28822D(L)T HY5DU281622D(L)T
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