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HY5S5B6ELF-HE 256MBit MOBILE SDR SDRAMs based on 4M x 4Bank x16 I/O

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Description

256MBit MOBILE SDR SDRAMs based on 4M x 4Bank x16 I/O Document Title 4Bank x 4M x 16bits Synchronous DRAM Revision History Revision No.0.1 0.2 0.3 1.
and is subject to change without notice.

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Datasheet Specifications

Part number
HY5S5B6ELF-HE
Manufacturer
Hynix Semiconductor
File Size
241.92 KB
Datasheet
HY5S5B6ELF-HE_HynixSemiconductor.pdf
Description
256MBit MOBILE SDR SDRAMs based on 4M x 4Bank x16 I/O

Features

* Standard SDRAM Protocol
* Programmable CAS latency of 1, 2 or 3 -25oC ~ 85oC Operation Package Type : 54ball, 0.8mm pitch FBGA (Lead Free, Lead) Internal 4bank operation Power Supply Voltage : VDD = 1.8V, VDDQ = 1.8V LVCMOS compatible I/O Interface Low Voltage interface to reduce I/O pow

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