* Standard SDRAM Protocol
* Programmable CAS latency of 1, 2 or 3 -25oC ~ 85oC Operation Package Type : 54ball, 0.8mm pitch FBGA (Lead Free, Lead) Internal 4bank operation Power Supply Voltage : VDD = 1.8V, VDDQ = 1.8V LVCMOS compatible I/O Interface Low Voltage interface to reduce I/O pow
HY5S5B6ELF-SE Datasheet (241.92 KB)
HY5S5B6ELF-SE
Hynix Semiconductor
241.92 KB
256mbit mobile sdr sdrams based on 4m x 4bank x16 i/o.
256MBit MOBILE SDR SDRAMs based on 4M x 4Bank x16 I/O Document Title
4Bank x 4M x 16bits Synchronous DRAM
Revision History
Revision No. 0.1 0.2 0.3 1.
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