* Standard SDRAM Protocol Internal 4bank operation
* Power Supply Voltage : VDD = 1.8V, VDDQ = 1.8V LVCMOS compatible I/O Interface Low Voltage interface to reduce I/O power Low Power Features - PASR(Partial Array Self Refresh) - AUTO TCSR (Temperature Compensated Self Refresh) - DS (Drive Streng
HY5S6B6x Datasheet (386.10 KB)
HY5S6B6x
Hynix Semiconductor
386.10 KB
(hy5s6b6d/l/s/f/p) 4banks x 1m x 16-bits sdram.
Document Title 4Bank x 1M x 16bits Synchronous DRAM Revision History w w w Revision No. 0.1 0.2 0.3 Initial Draft .D at h S a t e e 4U . .
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