HY5S7B6ALFP-6 Datasheet (Hynix Semiconductor) - 512MBit MOBILE SDR SDRAMs based on 8M x 4Bank x16I/O

HY5S7B6ALFP-6, 512MBit MOBILE SDR SDRAMs based on 8M x 4Bank x16I/O

and is subject to change without notice.

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Rev 1.1 / July.

2007 1 512Mbit (32Mx16bit) Mobile SDR Memory HY5S7B6ALF(P) Series DESCRIPTION The Hynix HY5S7B6ALF(P) is suited for non-PC application whi

HY5S7B6ALFP-6 Features

* Standard SDRAM Protocol Clock Synchronization Operation - All the commands registered on positive edge of basic input clock (CLK) MULTIBANK OPERATION - Internal 4bank operation - During burst Read or Write operation, burst Read or Write for a different bank is performed. - During burst Read or Write