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HY5S7B6ALFP-H

512MBit MOBILE SDR SDRAMs based on 8M x 4Bank x16I/O

HY5S7B6ALFP-H Features

* Standard SDRAM Protocol Clock Synchronization Operation - All the commands registered on positive edge of basic input clock (CLK) MULTIBANK OPERATION - Internal 4bank operation - During burst Read or Write operation, burst Read or Write for a different bank is performed. - During burst Read or Write

HY5S7B6ALFP-H General Description

and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev 1.1 / July. 2007 1 512Mbit (32Mx16bit) Mobile SDR Memory HY5S7B6ALF(P) Series DESCRIPTION The Hynix HY5S7B6ALF(P) is suited for non-PC application whi.

HY5S7B6ALFP-H Datasheet (656.38 KB)

Preview of HY5S7B6ALFP-H PDF

Datasheet Details

Part number:

HY5S7B6ALFP-H

Manufacturer:

Hynix Semiconductor

File Size:

656.38 KB

Description:

512mbit mobile sdr sdrams based on 8m x 4bank x16i/o.
512MBit MOBILE SDR SDRAMs based on 8M x 4Bank x16I/O Document Title 4Bank x 8M x 16bits Synchronous DRAM Revision History Revision No. 0.1 0.2 1.0 1..

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HY5S7B6ALFP-H 512MBit MOBILE SDR SDRAMs based 4Bank x16I Hynix Semiconductor

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